This invention relates generally to the area of system interconnect technology.
As CPU speeds approach the multi-gigahertz range, system designers increasingly focus on system interconnect as the primary bottleneck at the chip-to-chip, board-to-board, backplane and box-to-box levels. System interconnect has evolved from utilizing parallel I/O technology with source-synchronous clocking or system-synchronous clocking to multi-gigabit serial I/O with clock-data recovery (“CDR”). Channel aggregation bonds individual serial I/O lanes to create a multi-lane link, transcending the bandwidth limitations of single transceiver channels and providing the high bandwidth required by next generation serial protocols. However, various communication protocols have different functional requirements. At the same time, there is an increasing need for system designers to have flexibility in designing systems to work with one particular protocol versus another. Moreover, protocols continue to evolve, so there is a need for transceivers that can be reconfigured to meet the needs of future potential variations in high speed communication protocols. Such protocols may change during the product life of an integrated circuit (“IC”); therefore there is a need for a configurable transceiver design flexible enough to potentially accommodate such changes. Specifically, there is also a need to prove such flexibility in the context of a transceiver incorporating a lane based architecture for its Physical Coding Sublayer (“PCS”) circuitry.